Instructor:
Jeffrey Ashley Jr
Jeffrey Ashley Jr
281
Credits:
2.0
002
Building:
F Paul Anderson Tower
TBD
Room:
Rm.591
TBD
Semester:
Spring 2023
Start Date:
End Date:
Name:
Logical Design Lab
Requisites:
Prereq: EE 280
Class Type:
LAB
LEC
2:00 pm
TBD
4:50 pm
TBD
Days:
R
TBD
A laboratory involving the design and implementation of logic circuits. Combinational and sequential (both synchronous) design examples using small and medium scale integrated circuits. Lecture,one hour; laboratory, one three-hour session. .
A laboratory involving the design and implementation of logic circuits. Combinational and sequential (both synchronous) design examples using small and medium scale integrated circuits. Lecture,one hour; laboratory, one three-hour session. .
EE