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Hardware Descr Languages & Program Logic

Instructor:
Jeffrey Ashley Jr
Jeffrey Ashley Jr
582
Credits:
3.0
001
Building:
F Paul Anderson Tower
F Paul Anderson Tower
Room:
Rm.581
Rm.581
Semester:
Spring 2023
Start Date:
End Date:
Name:
Hardware Descr Languages & Program Logic
Requisites:

Prereq: EE/CS 380 and engineering standing.

Class Type:
LEC
LEC
2:00 pm
3:00 pm
4:50 pm
4:50 pm
Days:
W
F

A study of hardware description languages including netlists, VHDL and Verilog; their use in digital design methodologies including modeling techniques, design verification , simulation, synthesis, and implementation in programmable and fabricated logic media. Programmable logic topics include CPLD and FPGA architectures, programming technologies and techniques.

A study of hardware description languages including netlists, VHDL and Verilog; their use in digital design methodologies including modeling techniques, design verification , simulation, synthesis, and implementation in programmable and fabricated logic media. Programmable logic topics include CPLD and FPGA architectures, programming technologies and techniques.

EE